What is a Digital Computer?


A digital computer is a fast electronic calculating machine that accepts digitized input information, processes it according to a list of internally stored instructions, and produces the resulting output information.


The list of instructions is called a computer program, and the internal storage is called computer memory.




Types of Computers


Personal Computers. This is the most common computer which has found wide use in homes, schools, and business offices.


Workstations. Although still of desktop dimensions, these machines have a computational power which is significantly higher than that of personal computers. Workstations are often used in engineering applications, especially for interactive design work (CAD/CAM).


Mainframes. A large and powerful computer used for business data processing in medium to large corporations that require much more computing and storage capacity than workstations can handle.


Supercomputers. These are used for large-scale numerical calculations found in applications such as weather forecasting and aircraft design and simulation. In mainframes and supercomputers, the main functional units may comprise a number of separate and often large parts.


Functional Units of a Computer


In its simplest form, a computer consists of five functionally independent main parts: input, memory,arithmetic and logic, output, and control units.


Input Unit


The Input Unit accepts coded information from human operators or from other computers.


Examples:
Keyboard, joystick, mouse, input pen, touch screen, trackball, scanner, bar code readers, microphone, floppy disks, magnetic tapes, compact disks.


The Memory Unit – Primary Storage


Primary Storage or Main Memory (MM). This is where programs are stored during their execution. The MM is a fast memory capable of operating at electronic speeds.


The information in MM is often processed in groups of fixed size called words. The number of bits in a word is the word length of the computer. Typical word lengths range from 16 to 64 bits. The MM is organized so that the contents of one word, containing n bits, can be stored or retrieved in one basic operation.


Since programs must reside in MM during execution, MM is often referred to as the bottleneck in most computer operations.


The Memory Unit – Primary Storage


To provide easy access to any word in MM, a distinct address is associated with each word location. Addresses are numbers that identify successive locations.
... 0124,194,302 4,194,303 Address of 1st Memory Location Memory Location


MM is also known as random-access memory (RAM). RAM is a memory in which any location can be reached in a short, fixed amount of time.


The time required to access one word is the memory access time. For RAMs, this time is fixed, independent of the location of the word being accessed. It typically ranges from 10 to 100 nanoseconds for most modern computers.


Main Memory Divisions


MM is subdivided into the following:


1. Input Storage Area – this area accepts and stores the input data to be processed.


2. Working Storage Space – holds the data being processed as well the intermediary results of such processes.


3. Output Storage Area – maintains the final outputs or processed results of the operations.


4. Program Storage Area – holds the programs or processed instructions given by the user. It stores the entire program that is being executed.


Memory Unit – Secondary Storage


Secondary Storage or Auxiliary Storage. This is used when large amounts of data have to be stored (on a more permanent basis), particularly if some of the data need not be accessed very frequently. This is a storage medium that will hold data and program/sets of instructions even if the computer system is switched off.


Picture, if you can, how many filing cabinet drawers would be required to hold the millions of files of, say the tax records kept by the Bureau of Internal Revenue (BIR). The record storage rooms would have to be enormous. Computers on the other hand permit storage on tape or disk in extremely compressed form. Storage capacity is unquestionably one of the most valuable assets of the computer. Take a simple diskette for example, it can hold the equivalent of 500 printed pages and an optical disk (CD-ROM) can hold approximately the equivalent of 400 books.


Processing Unit


Processing Unit. Also called the Central Processing Unit (CPU) or Central Processor.
It contains a number of high-speed (10 times faster than MM) storage elements called registers that are used for temporary storage of frequently used operands. It is mandatory for data to be stored in a register before it can be processed.


The CPU is composed of the Arithmetic-Logic Unit (ALU) and the Control Unit (CU).


The ALU is where all arithmetic and logic operations and manipulation of numbers take place.


The CU is the nerve center of a computer. It controls the entire activity of the CPU. It controls and coordinates the order and execution of program instructions. It accesses instructions in sequence, interprets them and then directs their implementation.


The ALU is where all arithmetic and logic operations and manipulation of numbers take place.


The CU is the nerve center of a computer. It controls the entire activity of the CPU. It controls and coordinates the order and execution of program instructions. It accesses instructions in sequence, interprets them and then directs their implementation.


Output Unit


It sends processed results to the outside world.


Examples: Display screens, printers, plotters, modems, microfilms, synthesizers, high-tech blackboards, film recorders








Basic Operation of a Computer


The operation of a computer can be summarized as follows:


1. The computer accepts information in the form of programs and data through an input unit and stores it in memory.
2. Information stored in the memory is fetched, under program control, into an arithmetic and logic unit, where it is processed.
3. Processed information leaves the computer through an output unit.
4. All activities inside the machine are directed by the control unit.








Basic Concepts of Computer Architecture


Computer Architecture is the design of computers, including their instruction sets, hardware components, and system organization.


Most computers follow the Von Neumann Architecture, also known as the Stored Program Architectureor the Fetch-Decode-Execute Architecture.


Von Neumann architecture simply means that programs (together with data) are stored in main memory during execution.


Not all computers follow the Von Neumann architecture. Some examples are processor array architecture,multiprocessor architecture, dataflow architecture, and neural network architecture.








Types of Programming Language


The different types of programming languages are as follows:


1. Machine Language
2. Assembly Language
3. High-level Language
4. 4GL Language


Machine Language
The natural or primitive language that the computer actually understands. This programming language consists of 0’s and 1’s which makes programming very difficult.


Sample machine language program to add 5 and 3 (using the Intel microprocessor instruction set):


10111000
00000101
00000000
10111011
00000011
00000000
00010001
11011000


Assembly Language


A programming language that uses “abbreviations” or mnemonics in place of binary patterns in order to make the task of programming easier. Mnemonics are designed to be easy to remember and are a significant improvement over binary digits.


An assembly language program has to be converted to machine language before a computer can execute it. An assembler is a special program that translates assembly language mnemonics into machine language.


Sample assembly language program to add 5 and 3 (using the Intel microprocessor instruction set):


MOV AX, 05
MOV BX, 03
ADC AX, BX


High-Level Language


A programming language that uses English-like commands or instructions. High-level languages are the easiest to use and contains many complicated or advanced instructions. Also known as the third generation language (3GLs). Most 3GLs support structured programming.


A high-level language has to be converted to machine language before a computer can execute it. Acompiler is a special program that translates high-level language instructions into machine language.


Examples of High-level Languages:


1. FORTRAN (FORmula TRANslation)
2. COBOL (COmmon Business-Oriented Language)
3. BASIC (Beginner’s All-purpose Symbolic Instruction Code)
4. Pascal
Sample BASIC program to add 5 and 3:
LET A = 5
LET B = 3
LET C = A + B


Fourth Generation Language


A fourth-generation programming language (or 4GL) is a programming language designed with a specific purpose in mind such as the development of commercial business software. The process of software development had been much improved with modern block structured third-generation programming languages but it was still frustrating, slow, and error prone to program computers. This led to the first "programming crisis", in which the amount of work that might be assigned to programmers greatly exceeded the amount of programmer time available to do it. Meanwhile, a lot of experience was gathered in certain areas, and it became clear that certain applications could be generalized by adding limited programming languages to them.


The term 4GL, according to James Martin, was first used in his 1982 book, Applications Development Without Programmers. This refers to non-procedural high-level specification languages. Nevertheless, the great majority of users of 4GLs would describe themselves as programmers and most 4GLs allowed for (or required) system logic to be written in a proprietary macro language or in a 3GL.


All 4GLs are designed to reduce:
 Programming effort.
 The time it takes to develop software.
 The cost of software development.


They are not always successful in this task and sometimes result in inelegant and unmaintainable code. However, given the right problem the use of an appropriate 4GL can be spectacularly successful.
Some successful 4th-generation languages are:
 Database query languages
o SQL
o Oracle SQL*Plus
o Progress 4GL


 Report Generators:
o Oracle Reports
o LINC
o GEMBase
o BuildProfessional
o Informix-4GL
o Metafont
o RPG-II
o S
o IDL-PV/WAVE
o Gauss
o Mathematica








Advantages of High-level Languages


Advantages of using high-level languages over low-level languages:


1. Easy to Learn. Low-level languages are more cryptic than high-level language.


2. Predefined Functions. Most high-level languages provide many pre-defined functions and subroutines, thereby simplifying programming tasks.


3. Portability. Low-level languages are specific towards a certain processor. The instruction set of the Intel processors (IBM PC’s and compatibles) is very much different from the instruction set of the Motorola processors (Apple Macintosh).








Advantages of Low-level Languages


Advantages of using low-level languages over high-level languages:


1. Compact Code. Programs are executed in their machine language format. Programs written in a high-level language should still be compiled and translated to machine language. Most compilers are not optimized to generate compact code.


2. Speed. This is directly related to compact code. The shorter the code, the shorter the execution time of the program.


3. Flexible. Low-level language does not constrain the programmer to follow a certain programming convention (i.e. modularity) or a rigid coding constraint (i.e. the called routine should be placed before the calling routine).


Application programs are now more and more complex and test the high-level language to its limit. High-level programmers now use assembly language-based subroutines to augment the capabilities of high-level languages.


How to Fetch/Read Data or Instruction from MM


Von Neumann architecture requires that all programs together with data must be stored in main memory during execution. In the case of the processor, it should have a way to read or fetch the program to be executed from the main memory. Programs cannot be executed in the main memory because it is merely a storage device and does not have circuits that can process data as what processor can do.


In order to fetch/read an instruction or data from main memory:


1. The CPU first sends the address of the memory location to be read.


2. The CPU then issues or sends the read signal to the memory.


A control signal is needed in order to fetch the data from the main memory. The read signal that is generated by the control unit indicates the type of operation that is to be performed in the main memory. This operation makes a copy of the content of the given memory address.


3. The word is then read out of memory and is loaded into a CPU internal register.






How to Write/Store Data into MM


During the execution of an instruction or program, there are instances that data or operand needs to be stored into the main memory. How does the processor determine the location in the main memory where data is to be stored?


In order to store/write data into main memory:


1. The CPU first sends the address of the memory location to be written.


In writing data into the main memory, it is necessary that the location in the main memory where data is to be stored should be identified first.


2. The CPU then sends the write signal together with the data or word to be written to memory.


The write signal is generated by the control unit and it indicates a write operation. In this operation, the current content of the location will be lost.


Example 1
Example of a typical assembly language instruction:


MOV R0, LOCA


The above instruction is an assembly language data transfer instruction. Copy the contents at memory location LOCA into a register in the processor, R0. The source address is LOCA which is a location in the main memory. Memory locations are usually named in this manner. The destination address is R0 which is a register in the processor. For the purpose of discussion, all register names is preceded by letter R and a number.


The given instruction requires the performance of several steps:


1. The instruction must be transferred or fetched from the MM into the CPU.
2. The operand at LOCA must be fetched.
3. The operand is stored in register R0.


Example 2


Take a look at another example of a typical assembly language instruction:


ADD R0, LOCA


Add the operand at memory location LOCA to the operand in a register in the processor, R0 and place the result into register R0. This instruction adds two numbers one from the main memory and one from a register in the processor. This instruction requires the ALU for the addition process.


The given instruction requires the performance of several steps:


1. The instruction must be transferred or fetched from the MM into the CPU.
2. The operand at LOCA must be fetched and added to the contents of R0.
3. The resultant sum is stored in register R0.






Connections between the Processor and the MM


The PC (Program Counter) contains the memory address of the instruction to be executed. During execution, the contents of the PC are updated to point to the next instruction.


Every time that an instruction is to be executed, the program counter releases its contents to the internal bus and sends it to the memory address register.


The MAR (Memory Address Register) holds the address of the location to or from which data are to be transferred.


As can be seen from the figure above, the connection of the MAR to the main memory is one-way or unidirectional.


The MDR (Memory Data Register) contains the data to be written or read out of the addressed location.
During the fetch operation, the MDR contains the instruction to be executed or data needed during execution. In write operation, MDR contains the data to be written into the main memory.


The IR (Instruction Register) contains the instruction that is being executed.


Before the IR executes the instruction it needs to be decoded first. As soon as the content of the MDR is transferred to the IR, the decoding process commences. After decoding, execution of the instruction will take place.








Operating Steps


1. PC is set to point to the first instruction of the program (the operating system loads the memory address of the first instruction).
2. The contents of the PC are transferred to the MAR (which is automatically transmitted to the MM) and a Read signal is sent to the MM.
3. The addressed word is read out of MM and loaded into the MDR.
4. The contents of MDR are transferred to the IR. The instruction is ready to be decoded and executed.
5. During execution, the contents of the PC are incremented or updated to point to the next instruction.


If operand or data needed by the instruction resides in MM:


1. It will have to be fetched by sending its address to the MAR and initiating a read cycle.
2. When the operand has been read from MM into the MDR, it may be transferred from the MDR to the ALU.


If result is to be stored in MM:


1. The result is sent to the MDR.
2. The address of the location where the result is to be stored is sent to the MDR and a write cycle is initiated.


Example


Enumerate the different steps needed to execute the machine instruction


ADD LOCA, R0


Assume that the instruction itself is stored in the main memory at location INSTR, and that this address is initially in register PC. The first two steps might be expressed as:


1. Transfer the contents of register PC to register MAR.
2. Issue a READ command to the main memory, and then wait until it has transferred the requested word into register MDR.








CPU Instruction Execution Steps


Instruction execution in a CPU can now be summarized by the following steps:


1. Fetching the instruction from the memory into the instruction register.
2. Incrementing the PC to point to the next instruction to be executed.
3. Determining the type of instruction fetched (instruction decoding).
4. Determining the location of data in the memory. If the instruction uses data.
5. Fetching the required data into internal CPU registers.
6. Executing the instruction.
7. Storing the results in the designated locations.
8. Return to Step 1.


This is commonly referred to as the fetch-decode-execute cycle.








Bus Structure


A bus is a collection of wires that connect several devices within a computer system.
When a word of data is transferred between units, all its bits are transferred in parallel.


A computer must have some lines for addressing and control purposes.


Three main groupings of lines:


1. Data Bus. This is for the transmission of data.
2. Address Bus. This specifies the location of data in MM.
3. Control Bus. This indicates the direction of data transfer and coordinates the timing of events during the transfer


Single Bus Structure
All units are connected to a single bus, so it provides the sole means of interconnection.


Single bus structure has advantages of simplicity and low cost. Single bus structure has disadvantages of limited speed since usually only two units can participate in a data transfer at any one time. This means that an arbitration system is required and that units will be forced to wait. (This requires Time Domain Multiplexing or TDM, the transmission of different types of information on the same lines, but at different times.)


Only two units can actively use the bus at any given time.


Bus control lines are used to arbitrate multiple requests for the use of the bus.


Buffer Registers are used to hold information during transfers. These prevent a high-speed processor from being locked to a slow I/O device during a sequence of data transfers.




Two-Bus Structure


In the first configuration, the processor is placed between the I/O unit and the memory unit. The processor is responsible for any data transfer between the I/O unit and the memory unit. The processor acts as a “messenger.” In this structure, the processor performance and capability is not being maximized. Most of the time, the processor is doing data transfer between these units instead of performing more complex applications. Also, the processor is idle most of the time waiting for these slow devices.


In the second configuration, I/O transfers are made directly to or from the memory. A special purpose processor called peripheral processor or I/O channel is needed as part of the I/O equipment to control and facilitate such transfers. This special processor for the main memory is the direct memory access (DMA) controller. It allows main memory to perform data transfer between I/O units.








Memory Locations and Addresses


MM is organized so that a group of n bits can be stored or retrieved in a single basic operation.


The M addresses constitute the address space of the computer system.


Example: For the Intel 8088/86 Microprocessor


Address Space = 1,048,576 addresses or memory locations using binary encoding of addresses, 20 bits are needed to represent all addresses, 220 = 1,048,576


Parts of an Instruction


The contents of memory locations can represent either:


1. instructions
2. operands or data (numbers or characters)


An instruction usually contains two parts:


1. the part that specifies the operation to be performed (op-code field).
2. the part that may be used to specify operand addresses.


Examples:




1. 32-bit instruction


8 bits 24 bits
Operation Field Addressing Information




2. 16-bit instruction (8088/86)


10001011 11101100
MOV SP TO BP








Main Memory Operations


Fetch or Read. This transfers the contents of a specific MM location to the CPU. The word in the MM remains unchanged.


Read/Fetch Cycle:


1. CPU sends address of the desired location.
2. MM reads the data stored at that address and sends it to the CPU.


Store or Write. This transfers a word of information from the CPU to a specific MM location. This destroys the former contents of that location.


Write/Store Cycle:


1. CPU sends address of the desired location to the MM, together with the data to be stored into that location.
2. Data is written at desired location.








Instructions and Instructions Sequencing


Types of Instructions:


1. Data transfers between MM and CPU registers.
2. Arithmetic and logic operations on data.
3. Program sequencing and control.
4. I/O operations or transfers.








Notations


R1 ß [LOC]


The contents of memory location LOC are transferred into register R1.
C ß [A] + [B]


The operands in memory locations A and B are fetched from MM and transferred into the CPU, where they will be added in the ALU. Then the resulting sum is to be stored into memory location C in MM


Address Notations


Three-Address Instructions


ADD A, B, C A ß [B] + [C]
B and C = source operands


A = destination operands


- The operands in memory locations B and C are fetched from MM and transferred into the CPU, where they will be added in the ALU. Then the resulting sum is to be stored into memory location A in MM.


Two-Address Instructions


ADD A, B A ß [A] + [B]


- The operands in memory locations A and B are fetched from MM and transferred into the CPU, where they will be added in the ALU. Then the resulting sum is to be stored into memory location A in MM.


MOVE B, C B ß [C]


- The contents of memory location C are transferred into memory location B in MM.


A common convention used is to write two-operand instructions in the form:


operation destination, source






One-Address Notation


Since addition is a two-operand operation, an implicit assumption must be made regarding the location of one of the operands as well as the result.


A general purpose CPU register, usually called the accumulator, may be used for this purpose.


Examples:


ADD A ACC ß [A] + [ACC]
Add the contents of memory location A to the contents of the accumulator and place the sum into the accumulator.


LOAD A ACC ß [A]
Move the contents of memory location A into the accumulator.


STORE A A ß [ACC]
Move the contents of memory location A into the accumulator.


Examples
LOAD A ACC ß [A]
ADD B ACC ß [B] + [ACC]
STORE C C ß [ACC]




Zero-Address Instructions


Instructions where the locations of all operands are defined implicitly.


 Example:


 Inc (increment the accumulator by 1)


 Dec (decrement the accumulator by 1)








Two-Phase Procedure in Instruction Execution


Instruction Fetch


Instruction is fetched from MM location whose address is in the program counter. The instruction is then placed in the instruction register in the CPU.


Instruction Execute


The instruction in the instruction register is examined to determine which operation is to be performed. The CPU then performs the specified operation.




Instruction Execution and Straight-Line Sequencing


To begin the execution of this program, the address of its first instruction (i) must be placed into the PC.
The CPU control circuits automatically proceed to fetch and execute instructions, one at a time, in the order of increasing addresses. This is straight-line sequencing.
This program will add a list of n numbers. The addresses of the memory locations containing the nnumbers are symbolically given as NUM1, NUM2, . . ., NUMn, and the resulting sum is placed in memory location SUM.


History of Intel Microprocessor


The 4-bit Microprocessors


Intel released the world’s first p in 1771. The 4004 is a 4-bit p with maximum memory of only up to 4,096 4-bit memory locations (2,048 bytes). It only has 45 instructions and was used in very limited applications such as early video games and small p-based controllers.


The 8-bit Microprocessors


1. In 1772, Intel released the 8008 which is an 8-bit p capable of addressing 16,384 bytes and has 48 instructions. It can execute an ADD instruction in 20 s.


2. In 1773, Intel released the 8080. The 8080 can address a total of 65,536 bytes and can execute an ADD instruction in 2 s only.


3. In 1777, the 8085 was released. It addresses the same amount of memory as the 8080 but it can execute an ADD instruction in 1.3 s. It also has a built-in clock generator and system controller.


The 16-bit Microprocessors


In 1778, Intel released the 8086 p and a year later the 8088. Both are 16-bit p’s and can execute instructions in as little as 400 ns. Both can address a total of 1,048,576 bytes or 524,288 16-bit words.
These 16-bit microprocessors have multiplication and division instructions. These functions were not available in most 8-bit p’s.


The main difference between the 8086 and the 8088 is the size of their external data bus. The external data bus of the 8088 is only 8-bits wide while that of the 8086 is 16-bits wide (take note the internal data bus of the 8088 is 16-bits wide). The reason for this is that many designers still wanted to use the cheaper 8-bit support and peripheral chips in their 16- bit systems.


The 8088 was the p used by IBM in their Personal Computer (PC), the PC XT, and the Portable Computer.








Basic 8088/8086 Architecture


Bus Interface Unit (BIU). This is responsible for fetching an instruction, the operand of an instruction or data from the MM.
The bus interface unit is the part of the CPU that interfaces with the rest of the PC. Its name comes from the fact that it deals with moving information over the processor data bus, the primary conduit for the transfer of information to and from the CPU. It has bus controller that is responsible for responding to all signals that go to the processor, and generating all signals that go from the processor to other parts of the system.


Specifically, it has the following functions:
 instruction fetch
 instruction queuing
 operand fetch and storage
 address relocation
 bus control




The BIU is also responsible for generating bus control signals such as those for memory read or write and I/O read or write. These signals are needed for control of the circuits in the memory and I/O subsystems.


Instruction Pointer (IP). This is the program counter.


Prefetch Queue. The 8086/8088 prefetches the succeeding instructions while executing the current one.
The prefetch queue simply acts as a buffer between the instruction register and the bus controller. This unit helps improve system performance by eliminating some conflicts for the bus (bus contention).


Execution Unit (EU). This is responsible for executing the instructions.


The execution unit is responsible for decoding and executing all instructions. It consists of an ALU, status and control flags, eight general-purpose registers, temporary registers, and queue control logic.
The EU extracts instructions from the top of the queue in the BIU, decodes them, generates operand addresses if necessary, passes them to the BIU and requests it to perform the read or write bus cycles to memory or I/O, and performs the operation specified by the instruction on the operands. During execution of the instruction, EU tests the status and control flags and updates them based on the results of executing the instruction. If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted to the top of the queue.


When the EU executes a branch or jump instruction, it transfers control to a location corresponding to another set of sequential instructions. Whenever this happens, the BIU automatically resets the queue and then begins to fetch instructions from this new location to refill the queue.








Logical Memory


Logical memory is the name given to the memory viewed by the programmer.


The logical memory space is the same for both the 8086 and the 8088. It starts at memory location 00000H and extends to location FFFFFH. The logical memory is 8 bits wide.


A 16-bit word of memory begins at any byte address and extends for two consecutive bytes. For example, the word at location 00122H is stored at byte 00122H and 00123H with the least significant byte stored in location 00122H.








Physical Memory


The physical memory is the actual organization of the memory that the hardware designers see. The physical memory map of the 8088 is identical to its logical memory map.


The physical memory of the 8086 contains two banks of memory.


The advantage of this organization is that the 8086 can read or write a 16-bit word in one operation (provided the addresses of the data are even). The 8088 requires two reads or writes to transfer 16 bits of data.




Dedicated and General Use of Memory


Addresses 00000H to 00013H (20 memory locations) are dedicated while addresses 00014H to 0007FH (108 memory locations) are reserved.


 These 128 bytes or memory locations are used for storage or pointers to interrupt service routines.


Addresses FFFF0H to FFFFBH (12 memory locations) are dedicated for functions such as storage of the hardware reset jump instruction.


Addresses FFFFCH to FFFFFH (4 memory locations) are reserved for use with future products.








Register Structure of the 8086/8088


All forms of programming depend upon a clear understanding of the internal register structure of the p.


General Purpose Registers


General Purpose Registers. These are used in any manner that the programmer wishes. Each is addressable as a 16-bit register (AX, BX, CX, DX) or as two 8-bit registers (AH, AL, BH, BL, CH, CL, DH, and DL).


1. AX (Accumulator). This is often used to hold temporary result after an arithmetic and logic operation.


2. BX (Base). This is often used to hold the base address of data located in the memory.


3. CX (Count). This holds the count for certain instructions such as shift count (CL) for shifts and rotates, the number of bytes (CX) operated upon by the repeated string instructions, and a counter (CX) with the LOOP instruction.


4. DX (Data). This holds the most significant part of the product after a 16-bit multiplication and the most significant part of the dividend before a division.








Pointer and Index Registers


Pointer and Index Registers. Although the pointer and index registers are also general purpose in nature, they are more often used to index or point to the memory location holding the operand data for many instructions.


1. SP (Stack Pointer). This is used to address data in a LIFO (last-in first-out) stack memory. This occurs most often when the PUSH and POP instructions are executed.


2. BP (Base Pointer). This is often used to address an array of data in memory.


3. SI (Source Index). This is used to address source data indirectly for use with string instructions.


4. DI (Destination Index). This is normally used to address destination data indirectly for use with the string instructions.








Status Register or Processor Status Word


Status Register or Processor Status Word. This contains 16 bits, but 7 of them are not used. Each bit in the PSW is a flag. These flags are divided into the conditional flags (they reflect the result of the previous operation involving the ALU) and the control flags (they control the execution of special functions).


The conditional flags are:


1. Sign Flag (SF) - b7
This is equal to the MSB of the result of the previous operation. 0 if positive, 1 if negative.


2. Zero Flag (ZF) - b6
This is set to 1 if the result of the previous operation is zero and 0 if the result is nonzero.


3. Parity Flag (PF) - b2
This is set to 1 if the low-order 8 bits of the result of the previous operation contain an even number of 1s. Otherwise, it is reset to 0.


Conditional Flags_(cont…)


4. Carry Flag (CF) - b0
An addition causes this flag to be set to 1 if there is a carry out of the MSB, and a subtraction causes it to be set to 1 if a borrow is needed.


5. Overflow Flag (OF) - b11
This is set to 1 if an overflow occurs, i.e., a result is out of range. More specifically, for addition this flag is set to 1 when there is a carry into the MSB and no carry out of the MSB or vice-versa. For subtraction, it is set to 1, when the MSB needs to borrow and there is no borrow from the MSB, or vice-versa.


6. Auxiliary Carry Flag (AF) - b4
This flag is used exclusively for BCD arithmetic. It is set to 1 if there is a carry out of bit 3 (b3) during an addition or borrow by bit 3 during a subtraction.








Example 1


1.
0010 0011 0100 0101
+ 0011 0010 0001 1001
0101 0101 0101 1110


SF = 0 ZF = 0 PF = 0 CF = 0 AF = 0 OF = 0


In this example, the sign flag (SF) is 0 since the MSB is 0, the zero flag (ZF) is 0 since the result is nonzero, the parity flag (PF) is 0 since the low-order 8 bits or the first 8 bits from the least significant bit (LSB) has odd number of ones, the carry flag (CF) is 0 since there is no carry out of the most significant bit (MSB), the auxiliary flag (AF) is 0 since there is no carry out of bit 3 and overflow flag (OF) is 0 since there is no carry into the MSB and no carry out of the MSB.


2.
0101 0100 0011 1001
+ 0100 0101 0110 1010
1001 1001 1010 0011


SF = 1 ZF = 0 PF = 1 CF = 0 AF = 1 OF = 1


In this example, the sign flag (SF) is 1 since the MSB is 1, the zero flag (ZF) is 0 since the result is nonzero, the parity flag (PF) is 1 since the low-order 8 bits or the first 8 bits from the least significant bit (LSB) has even number of ones, the carry flag (CF) is 0 since there is no carry out of the most significant bit (MSB), the auxiliary flag (AF) is 1 since there is a carry out of bit 3 (b3) and overflow flag (OF) is 1 since there is a carry into the MSB and no carry out of the MSB.








Example 2
1.
0101 0100 0011 1001
- 0100 0101 0110 1010
1001 1001 1010 0011


SF = 1 ZF = 0 PF = 1 CF = 0 AF = 1 OF = 1


In this example, the sign flag (SF) is 1 since the MSB is 1, the zero flag (ZF) is 0 since the result is nonzero, the parity flag (PF) is 1 since the low-order 8 bits or the first 8 bits from the least significant bit (LSB) has even number of ones, the carry flag (CF) is 0 since there is no borrow by the most significant bit (MSB), the auxiliary flag (AF) is 1 since there is a borrow by bit 3 (b3) and overflow flag (OF) is 1 since there is a borrow by the MSB and no borrow from the MSB.


2.


0001 0010 0011 0100
- 0100 1010 1110 0000
1100 0111 0101 0100


SF = 1 ZF = 0 PF = 0 CF = 1 AF = 0 OF = 0


In this example, the sign flag (SF) is 1 since the MSB is 1, the zero flag (ZF) is 0 since the result is nonzero, the parity flag (PF) is 0 since the low-order 8 bits or the first 8 bits from the least significant bit (LSB) has odd number of ones, the carry flag (CF) is 1 since there is a borrow by the most significant bit (MSB), the auxiliary flag (AF) is 0 since there is no borrow by bit 3 (b3) and overflow flag (OF) is 0 since there is a borrow by the MSB and a borrow from the MSB.












Example 3


Perform the following arithmetic operation and determine the state of the conditional flags.


1. 70A3H – E757H
2. FE58H + 01A8H


The first thing to do is to convert the given hexadecimal numbers to their equivalent binary values (disregard the letter H; it only refers to the number system used which is hexadecimal). Then, perform the indicated arithmetic operation. After that, determine the values of the conditional flags.








Control Flags


The control flags are:


1. Direction Flag (DF) - b10


This flag is used by string manipulation instructions. If clear, the string is processed from its beginning with the first element having the lowest address. Otherwise, the string is processed from the high address towards the low address.


2. Interrupt Enable Flag (IF) - b9


If set, a certain type of interrupt (a maskable interrupt) can be recognized by the CPU; otherwise, these interrupts are ignored.


3. Trap Flag (TF) - b8
If set, the 8086/8088 will enter into a single-step mode. In this mode, the CPU executes one instruction at a time.








Segment Registers and Memory Segmentation


Even though the 8086/8088 has a 1MB memory address space, not all this memory can be active at any one time.


 The MM can be partitioned into 64K (65,536) byte segments where each segment represents an independently addressable unit of memory consisting of 64K consecutive byte-wide storage locations.


 Each segment is assigned a base address that identifies its starting point, that is, its lowest-addressed byte storage location.












Generating a Memory Address


A logical address in the 8086/8088 is identified by a segment (its base address) and an offset. The offset identifies the distance in bytes that the storage location of interest resides from this starting address.


Both segment base address and offset are 16 bits long. Therefore, the lowest-addressed byte in a segment has an offset of 0000H and the highest-addressed byte has an offset of FFFFH.


 However, the physical addresses that are used to access memory are 20 bits long. The generation of the physical address involves combining a 16-bit offset value and a 16-bit segment base address value that is shifted-left by 4 bits with its LSB’s being filled with 0s.








Example 1
Determine the physical address of the following:
1. Segment Base Address = 1234H
Offset Address = 0022H


Computing for the physical address is just getting the sum of the physical segment base address and the offset address. The physical segment base address is the segment base address shifted 4 bits to the left or simply appends 0 before the least significant bit (LSB).


If the segment base address is 1234H then the physical segment base address is 12340H.


Physical Segment Base Address 12340H
+ Offset Address + 0022H
Physical Address = 12362H


Note: Remind the students that hexadecimal addition is different from the usual addition process. The students may convert the given hexadecimal values to binary numbers first and then perform the addition process and then convert it back to the hexadecimal notation.


Take note that the offset address is sometimes called the effective address.


 Logical addresses are often written following the segment base address:offset format.








Example 2
2. Segment Base Address = 123AH
Offset Address = 341BH


Computing for the physical address:
Physical Segment Base Address = 123A0H
+ Offset Address = 341BH
Physical Address = 157BBH